1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to signal value storage circuitry incorporating transition error detecting mechanisms for use within data processing systems.
2. Description of the Prior Art
It is known to provide data processing systems including signal storage circuitry. This storage circuitry could take a wide variety of different forms, such as master/slave latches, flip-flops, registers and alike. Such signal value storage circuitry is used to capture and store state within the data processing system. These stored signals may represent data or control information. Signal values typically propagate between signal value storage circuitry and pass through processing circuitry disposed between these instances of signal value storage circuitry. A clock signal is used to regulate the passing of signal values between the signal value storage circuitry.
It is known from WO-A-2004/084072 to provide signal value storage circuitry including error detection circuitry which detects whether or not the signal value stored in that signal value storage circuitry was captured too early and accordingly does not represent the true signal value which should have been captured and passed on to subsequent processing circuitry. If an error is detected in this way, then error correction mechanisms are triggered and corrective action(s) taken.
FIG. 1 of the accompanying drawings schematically illustrates an example of a clock signal used for regulating capture of a signal value into signal value storage circuitry. The signal value is captured at rising edge of the clock signal. If a transition in the signal value that is to be captured arrives at the signal valve storage circuitry before the rising edge, then the correct signal value will be captured at the rising edge and no error occurs. However, if the transition in the signal does not arrive until after the rising edge in the clock signal, then an incorrect value will have been captured at that rising edge and an error will have occurred. An error detection window constituting a time after the rising edge of the clock signal is provided and any transitions within the signal arriving at the signal value storage circuitry occurring within this error detection window indicate a late arriving signal and that an error has occurred. It will be appreciated that the error detection window cannot grow too large otherwise it might incorrectly identify the arrival of a correct subsequent signal value at the signal value storage circuitry as a late transition in the preceding signal value.
The error detection window is triggered relative to the rising edge of the clock which controls the storage of the signal value into the signal value storage circuitry. One requirement of the transition detection circuit is that any transition (including glitches) which could cause either an incorrect state value to be latched, or metastability, is flagged as an error. This has the consequence that the error transition circuits satisfy constraints relating to both sensitivity (in order to to be able to react to glitches), and minimum delay (in order to be able to guarantee that the effective timing error detection window always covers the setup time of the storage circuit). If the delay of the transition circuit is more than the minimum required, then the error detection becomes pessimistic, and signal transitions which occur before the setup time of the storage element can still be flagged as errors. As process geometry for forming integrated circuits decrease in size, it becomes increasingly difficult to provide transition detection circuitry which satisfies both sensitivity and uniform delay constraints.
One technique, which can somewhat alleviate these design constraints, is to generate a time shifted version of the clock signal, and use this to control the action of the transition detection circuit. This has the effect of allowing more delay in the transition circuit without increasing pessimism, which in turn allows different tradeoffs for sensitivity and delay uniformity. However, there is a power consumption penalty involved in providing such a time shifted clock signal for the purpose of controlling the transition detection circuitry and this renders this possibly unattractive.